With rapid development of integrated circuit (IC) manufacturing technology, size of semiconductor devices in an IC, especially size of metal-oxide-semiconductor (MOS) devices, has been shrinking continuously in order to meet the miniaturization and integration requirement of IC development. During the continuous miniaturization of MOS transistor devices, existing process of using silicon oxide or silicon oxynitride as a gate dielectric layer is faced with challenges. A transistor formed by using silicon oxide or silicon oxynitride as the gate dielectric layer has problems such as increase of leakage current and diffusion of impurities. Thus, the threshold voltage of the transistor is often affected, and the performance of the semiconductor device is affected accordingly.
To solve the above problems, transistors formed using high-K gate dielectric layer and metal gate, i.e., high-K metal gate (HKMG) transistors, have been proposed (K refers to dielectric constant). A high-K metal gate transistor uses a high-K material to replace the commonly-used gate dielectric material such as silicon oxide or silicon oxynitride. Thus, at the same time of reducing the size of a transistor, the generated leakage current can be reduced, and the performance of the transistor can be improved.
In particular, FIG. 1 depicts a cross-sectional view of an existing high-K metal gate transistor. As shown in FIG. 1, the transistor includes a dielectric layer 105 and a gate structure 110 on the surface of a substrate 100. The top surface of the gate structure 110 is leveled with the top surface of the dielectric layer 105. The gate structure 110 includes a high-K gate dielectric layer 101 on the surface of the substrate 100, a metal gate 103 on the surface of the high-K gate dielectric layer 101, and sidewall spacers 104 on the surface of the substrate 100 at both sides of the high-K gate dielectric layer 101 and the metal gate 103. A source region/drain region 106 is located in the substrate 100 at both sides of the gate structure 110.
For illustrative purposes, FIG. 1 shows that the top of the sidewall spacers 104 is leveled with the top surface of the dielectric layer 105. In practice, the top of the sidewall spacers 104 is not necessarily always leveled with the top surface of the dielectric layer 105. Before the forming of the metal gate 103 and the high-K gate dielectric layer 101, the top of the sidewall spacers 104 is often not leveled with the top surface of the dielectric layer 105.
However, performance of the high-K metal gate transistor formed by the existing technology is often unstable. The disclosed methods and structures are directed to solve one or more problems set forth above and other problems.